Monday, 24 August 2020

CS501-Advanced Computer Architecture Quiz MCQs Lecture 23-45 Finalterm Objective Questions | SUPERSTARWEBTECH



CS501-Advanced Computer Architecture Quiz MCQS #Objective #Questions #FinalTerm

1. In which one of the following methods, does the CPU poll to identify the interrupting module and branches to an interrupt service routine on detecting an interrupt?
  • Daisy Chain
  • Software Poll ✔
  • Multiple interrupt lines
  • All of the given
2. Human works with base 10 and computers work with base ___
  • 8
  • 10
  • 2 ✔
  • 16
3. ___ is an electrical pathway through which processor communicates with the internal and external devices attached to the computer.
  • Computer Bus ✔
  • Hazard
  • Memory
  • Disk
4. An interface that can be used to connect the microcomputer bus to ___ is called an I/O Port.
  • Flip Flops
  • Memory
  • Peripheral devices ✔
  • Multiplexers
5. Which is the last instruction of the ISR that is to be executed when the ISR terminates?
  • IRET ✔
  • IRQ
  • INT
  • NMI
6. ___ is the simplest form for representing a signed number
  • Biased Representation
  • Diminished Radix Compliment Form
  • Sign Magnitude Form ✔
  • None
7. Raid Level ___ is not a true member of the RAID family
  • 0 ✔
  • 2
  • 3
  • 4
8. Which I/O technique will be used by a sound card that may need to access data stored in the computer's RAM?
  • Programmed I/O
  • Interrupt driven I/O
  • Direct memory access (DMA) ✔
  • Polling
9. Where does the processor store the address of the first instruction of the ISR?
  • Interrupt vector ✔
  • Interrupt request
  • Interrupt handler
  • All of the given
10. When a particular sector is found, the data is transferred to ___
  • RAM 
  • I/O module ✔
  • Cache memory
  • Instruction register
11. ___ is the time needed by the CPU to recognize (not service) an interrupt request.
  • Interrupt Latency ✔
  • Response Deadline
  • Timer delay
  • Throughput
12. The ___ is w-bit wide and contains a data word, directly connected to the data bus which is b-bit wide memory address register (MAR).
  • memory buffer register (MBR) ✔
  • Program Counter (PC)
  • Instruction Register (IR)
  • Memory address register (MAR)
13. Adding an address pin to a memory chip increases the capacity of memory by a factor of ___
  • 1.5
  • 2 ✔
  • 2.5
  • 3
14. The main issue/s in error control is/are ___
  • Detection of Error
  • Correction of Error
  • Both Detection of Error and Correction of Error ✔
  • Avoidance of Error
15. Along with information bits, we add up another bit, which is called?
  • Start bit
  • Header bit
  • Parity bit ✔
  • Stop bit
16. The conversion of numbers from a representation in one base to another is known as ___
  • Radix Conversion ✔
  • Number Representation
  • Decimal Representation
  • Hexadecimal Representation
17. Why DMA is faster than Programmed I/O technique because?
  • DMA transfers data directly using CPU
  • DMA transfers data directly without using CPU ✔
  • DMA uses buffers with CPU
  • DMA uses interrupted driven I/O
18. Multiple copies of the same data can exist in memory hierarchy simultaneously. The Cache needs updating mechanishm to prevent old data values from being used. This is the problem of ___
  • Cache Miss
  • Dirty Bit
  • Cache Coherence ✔
  • Write Allocate
19. ___ is the simplest form for representing a signed number
  • Biased Representatin
  • Diminished Radix Compliment Form
  • Sign Magnitude Form ✔
  • None
20. ___depends upon the present position of the head and the position of the required sector.
  • Direct Memory Access ✔
  • Execution Time
  • Throughput
  • Seektime
21. In which technique does the hardware directly access host memory for reading or writing independent of CPU?
  • Direct Memory Access (DMA) ✔
  • Programmed I/O
  • Interrupt driven I/O
  • Polling